University of California
Dept. of Computer Science
Riverside, CA 92521
dalton@cs.ucr.edu
| |
Dalton Project University of California Dept. of Computer Science Riverside, CA 92521 dalton@cs.ucr.edu |
 |
The Intel 8051 is an 8-bit micro-controller. This micro-controller is capable of addressing 64K of program and 64K of data memory. The implementation below is written in Synthesizable VHDL (at least by Synopsys and Xilinx,) and models the actual Intel implementation rather closely, e.g., it is 100% instruction compatible. Visit this page for latest information and upgrades, and keep in mind that we tend to make frequent revisions. Do not hesitate to contact us regarding questions or comments. Needless to say, we do not, nor does the University of California at Riverside, provide any kind of warrantee for anything you read or download from this page. |
We plan on, slowly, removing all the above limitations/shortcomings. We would also appreciate any help from people willing to contribute to this design. Please contact us.
Here is a short description of the related files.
File |
Description |
| i8051_lib.vhd | Defines a package that is used in all the VHDL files of the 8051 model. This package defines commonly used constants. |
| i8051_alu.vhd | Model of an ALU that performs 8051 specific arithmetic. This model is described behaviorally as a combinational logic block. |
| i8051_dec.vhd | Model of a decoder that decodes the non-uniform 8051 instructions into uniform representations, i.e., enumerated codes. This model is described as a data-flow implementing a combinational logic block. |
| i8051_ram.vhd | Model of 128 bytes of RAM, specific to 8051, e.g., bit-addressable. This model is described behaviorally as a sequential logic block. |
| i8051_rom.vhd* | Model of up to 64K bytes of ROM, specific to 8051. This model is automatically generated behaviorally, as a sequential logic block, using i8051_mkr.c. |
| i8051_ctr.vhd | Model of the core 8051 processor. This model is described behaviorally as a sequential logic block. |
| i8051_dbg.vhd | This entity is there for debugging only. Currently, it outputs a trace of each instruction that is executed. |
| i8051_all.vhd | Model of a complete 8051 micro-controller. This model structurally combines the above logic blocks. |
| i8051_tsb.vhd | Model of a test-bench for the 8051 micro-controller. This model is described behaviorally as an I/O-less sequential logic block. (It merely resets, then clocks the micro-controller for ever.) |
| i8051_mkr.c | Program to convert an Intel 8051 HEX file into a ROM model, i.e., generates i8051_rom.vhd. You will need to compile this C/C++ file, say, gcc -Wall i8051_mkr.c, then run it with your HEX file as a command line argument to it, e.g., a.out myfile.hex. |
| syn_alu.inc, syn_dec.inc, syn_ram.inc, syn_rom.inc, syn_ctr.inc | Include files, specific to dc_shell, that will synthesize the above VHDL models down to gate. |
| zsim.scr, zsyn.scr | Script files that simulate/synthesize everything. |
* Up to 4K ROM model of sort.c program.
Here is some statistics that you may find interesting. These are obtained by synthesizing the models down to gate, using medium mapping effort. Library binding is to lsi_10k, supplied by Synopsys. No area/delay constraints have been specified. Machine in use has dual 200 MHz Ultra Sparc II processors.
Model |
I/O Ports (bit) |
Combinational Area (nand-gate) |
Sequential Area (nand-gate) |
Critical Path Length (ns) |
Maximum Clock Speed (MHz) |
Synth. Time (min) |
| I8051_ALU | 50 |
1992 |
0 |
101.3 |
9.8 |
2 |
| I8051_DEC | 18 |
586 |
0 |
44.5 |
22.4 |
2 |
| I8051_RAM | 31 |
4958 |
12370 |
1.25 |
800 |
20 |
| I8051_ROM* | 23 |
1047 |
56 |
1.37 |
729 |
12 |
| I8051_CTR | 118 |
2044 |
1246 |
1.47 |
680 |
13 |
| I8051_ALL** | 66 |
10677 |
13672 |
52.12 |
19 |
49 |
* Up to 4K ROM model of sort.c program.
** Estimated values.
This is our collection of test-files, in C format, of course. Our test strategy has been to write programs (C), compile them into Intel 8051 binaries (HEX), convert these into ROM models (VHDL), then, simulate and observe the behavior. Take a look at this table to get a feel for how well these test programs stress the 8051!
C |
HEX |
Size (byte) |
Simulation Time (ns) |
Signal Trace |
| negcnt.c | negcnt.hex | 39 |
270,000 |
P0 = 64, 65, 66, 67, 68, 69, 70, 71, 72, 73 |
| gcd.c | gcd.hex | 51 |
327,000 |
P0 = 36, 25, 14, 3, 1 |
| int2bin.c | int2bin.hex | 60 |
500,000 |
P0 = 0, 1, 0, 1, 0, 1, 0, 1 |
| cast.c | cast.hex | 127 |
870,000 |
P0 = 01H, P1 = 23H, P2 = 45H, P3 = 67H |
| divmul.c | divmul.hex | 210 |
370,000 |
P0 = 10, 4, 134 |
| fib.c | fib.hex | 305 |
1,042,000 |
P0 = 1, 1, 2, 3, 5, 8, 13, 21, 34, 55 |
| sort.c | sort.hex | 544 |
3,600,000 |
P0 = 0, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 |
| sqrt.c | sqrt.hex | 1121 |
4,000,000 |
P0 = 9, P1 = 16, P2 = 25, P3 = 5 |
Here is were you'll find the latest (as well as older to oldest) source code in tared/gziped format.
Archive |
Version |
Date |
Notes |
| source_2.4.tar.gz | 2.4 |
11/23/1999 | Fixed a bug in i8051_mkr.c that caused it to fail when non keil compiled hex files were being loaded. (Many thanks to Lars Wehmeyer who found and fixed the error and then sent us a patch.) |
| source_2.3.tar.gz | 2.3 |
11/19/1999 | Converted the i8051_mkr.cc file to i8051_mkr.c, i.e., a pure C file for greater portability. Fixed a bug in the I8051_ALU entity, more specifically, the divider unit. Removed the reference to I8051_LIB in the testbench (not needed there). |
| source_2.2.tar.gz | 2.2 |
9/15/1999 | Fixed a harmless warning when compiling i8051_mkr.cc. For consistency with the material on this page, made sort.hex the default program in i8051_rom.vhd. |
| source_2.1.tar.gz | 2.1 |
8/15/1999 | First released version. |
Last Updated 11/23/1999
Published by NewIT Labs